Problem: I have a problem with this SystemVerilog code. Here is the code: module mult ( multiplicand, multiplier, Product, clk, clear, Startm, endm ); input [31:0] multiplicand; input [31:0] multiplier ; input clk; input clear; input Startm; output ... of 64 bits using the Booth's algorithm. This error occur: always_comb construct does not infer purely combinational logic Why does this happens?

asked
May 4
anika11
32.2k points